The inventive concept relates to fin field effect transistors and methods of fabricating the same.
As the size of the gate of a transistor becomes smaller, problems such as short channel effects may occur. It may be difficult to highly integrate a MOS transistor using MOS transistor fabrication techniques with a bulk silicon substrate. Thus, research has been done on the use of a silicon-on-insulator (SOI) substrate for MOS transistors. However, since the body of a MOS transistor using the SOI substrate is not connected to a substrate (i.e., the body silicon floats), the performance of the device may be reduced due to the floating body effect and due to low heat conduction.
Recently, a fin field effect transistor has been proposed. The fin field effect transistor may correspond to a double-gate transistor of which a gate electrode is disposed on both sides of a channel. Since the gate electrode of the fin field effect transistor is on both sides of the channel, the control characteristic of the gate electrode may be improved. Thus, leakage current between a source and a drain in the fin field effect transistor may be improved compared to a conventional single gate transistor, such that a drain induced barrier leakage (DIBL) characteristic of the fin field effect transistor may be improved. Additionally, since the threshold voltage may be changed by having the gate electrode on both sides of the channel, the on-off characteristic of the channel may be improved compared to the conventional single gate transistor and short channel effects may also be suppressed.
However, as the fin field effect transistor becomes more highly integrated due to the reduced size of the device, it may be more difficult to improve current driving ability of the fin field effect transistor.